作者JasonZZZ (吃吃吃)
看板Oversea_Job
標題[北美] Job open: Design Verification Engr
時間Fri Nov 4 10:17:24 2011
請在美國當地的朋友寄email來就可以了
從台灣寄來的除非你本人正在美國
不然我老闆應該是不會出國際機票的
Job Title
Design Verification Engineer – Entry Level
Job Description
In this position, the individual will participate in the logic design
and verification of NAND Flash memory products.
Main responsibilities include:
- Development of SystemVerilog TestBench for NAND Flash chips
- Full-chip verification on Flash memory projects with SVTB.
Other responsibilities include:
- Support of SystemVerilog Assertion
- Behavioral modeling in SystemC and C++
- Support of design and verification methodology enhancements
Job Qualification:
Recent or Dec. 2011 graduation with one of following qualifications:
- MS EE with logic design Verilog RTL focus; as well as C++ knowledge
- MS CS/CE with strong C++ skills; as well as knowledge in Verilog &
logic design
Job Location Milpitas, CA
SanDisk Corporation
SanDisk is the world's largest supplier of innovative flash memory data
storage products and we offers a highly competitive compensation package
and great benefits, which include Stock Options, ESPP, matched 401 (K),
comprehensive insurance and tuition reimbursement.
SanDisk is an equal opportunity employer.
please email your resume to:
chih-hao.yu@sandisk.com
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◆ From: 63.163.107.100
推 ccchen:只找 entry level 的嗎?有朋友多年經驗想找 11/04 10:47
→ TripleC:之前原po在版上找過很多次senior的哦 11/04 12:01
→ JasonZZZ:有多年經驗的也在找 請歡迎轉寄 11/04 13:29
推 yohowo:貴公司缺這麼大阿..好常找人毆 11/04 14:04
→ JasonZZZ:verification的似乎不太好找,剛好team又要擴大 11/05 01:15
推 ccchen:最近業界找 verification 的比 design 多不少 11/05 03:35
→ blackacre:Verification是永遠不會失業的 11/05 05:18
→ TripleC:verification面對的是印度大軍吧... 11/05 10:01