Matthew Dillon wrote:
> :Are you talking about VHDLs here or more the formal method side (Maude,
> :ACL2, Z Notation, VDM)?
> :
> :--
> :Jeroen Ruigrok van der Werven <asmodai(at)wxs.nl> / asmodai / kita no mono
>
> I was thinking VHDL and the like.
>
> -Matt
> Matthew Dillon
> <dillon@backplane.com>
This is very likely exactly what some of the compiling VHDL simulators
do. If someone did this it would really screw up the academic world,
where in every class we use VHDL they tell us first that VHDL should not
be viewed as programming. :)
-Mike (who currently has a project to finish in VHDL)