下面是在做4-bit除法器的程式碼,在11/2=5餘1的測試中
在modelsim進行simulate Behavioral Model時,接近我想要的動作
但是,在r_reg=00101100時,下一動作居然是00001000,不是我想要的00001100或00011000
檢查半天還是找不出來......
另外,不知為什麼用Simulate Post-Place&Route VHDL Model模擬時,又跟
simulate Behavioral Model有很大的不同,而且不是我想要的結果....
到底是哪邊寫錯或觀念錯誤呢?可否請高手指點,感謝...
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entity sas is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end sas;
architecture Behavioral of sas is
signal R_reg : std_logic_vector(7 downto 0);
signal Q_reg : std_logic_vector(3 downto 0);
signal A_reg : std_logic_vector(3 downto 0);
signal B_reg : std_logic_vector(3 downto 0);
signal sel : std_logic_vector(1 downto 0);
signal ent : std_logic;
signal cnt : integer range 0 to 3;
begin
process (CLK,RST)
begin
if (CLK'event and CLK = '1') then
if RST = '1' then
R_reg <= "00000000";
Q_reg <= "0000";
A_reg <= "0000";
B_reg <= "0000";
ent <='0';
cnt <= 0;
elsif (A /= A_reg) or (B /= B_reg) then
sel <= "00";
A_reg <= A;
B_reg <= B;
end if;
case sel is
when "00" =>
R_reg(3 downto 0) <= A;
sel <= "01";
cnt <= 0;
when "01" =>
R_reg(7 downto 0) <= R_reg(6 downto 0) & '0';
Q_reg(3 downto 1) <= Q_reg(2 downto 0);
if R_reg(7 downto 4) < B then
Q_reg(0) <= '0';
cnt <= cnt + 1;
else
Q_reg(0) <= '1';
R_reg(7 downto 4) <= R_reg(7 downto 4) - B;
end if;
if cnt = 3 then
sel <= "10";
else
sel <= "01";
end if;
when others =>
R <= R_reg(7 downto 4);
Q <= Q_reg;
end case;
end if;
end process;
end Behavioral;
--
※ Origin: 楓橋驛站<bbs.cs.nthu.edu.tw> ◆ From: 210-58-7-53.cm.dynamic.apol.com.tw