[問題]請問Synthesis的問題

[finalhaven (俺式最終天堂!!)]

這是我的VERILOG CODE
=================================================================

module FIFO(
Data_out,
Data_in,
stack_empty,
stack_full,
clk, rst,
write_to_stack,
read_from_stack
);
parameter stack_width = 12;
parameter stack_height = 8;
parameter stack_ptr_width = 3;

output [stack_width -1:0] Data_out;
output                   stack_empty,stack_full;
input  [stack_width -1:0] Data_in;
input                    clk,rst;
input                    write_to_stack, read_from_stack;
reg    [stack_ptr_width -1:0] read_ptr,write_ptr;

reg    [stack_ptr_width:0]   ptr_diff;
reg    [stack_width-1:0] Data_out;
reg    [stack_width-1:0] stack[stack_height-1:0];

assign stack_empty = (ptr_diff == 0)? 1'b1:1'b0;
assign stack_full=(ptr_diff == stack_height)? 1 'b1:1'b0;

always@(posedge clk or posedge rst)
begin:data_transfer

if(rst)Data_out=0;
else if((read_from_stack) && (!write_to_stack) && (!stack_empty))

        Data_out <= stack [read_ptr];

(Cannot mix blocking and non blocking assignments on signal <Data_out>.)
不知為何錯誤的訊息，指在上面Data_out那一行....

else if((write_to_stack)&&(!read_from_stack)&&(!stack_full))

        stack [write_ptr] <= Data_in;

end

always@(posedge clk or posedge rst)
begin:update_stack_ptrs

if(rst)

  read_ptr <=0;
  write_ptr <=0;
  ptr_diff <=0;
 end

 else if((write_to_stack)&&(!stack_full)&&(!read_from_stack))
         begin
          write_ptr <= write_ptr +1;
          ptr_diff<=ptr_diff +1;
         end
 else if((!write_to_stack)&&(!stack_empty)&&(read_from_stack))
         begin
          read_ptr <= read_ptr + 1;
          ptr_diff <= ptr_diff-1;
         end

 end
 endmodule

=========================================================
此CODE某書裡面的CODE
想做STACK憶體練習
我用ISE 9.1i版本去合成
就會跑出上面Data_out那個錯誤
不知道為甚麼

--
當在跑向終點的漫長旅程上，請不要忘記最初起點的夢想!

--
※ 發信站: 批踢踢實業坊(ptt.cc) 
◆ From: 122.116.21.173
推 espreesso:Cannot mix blocking and non blocking assignments
→ espreesso:if(rst)Data_out=0;   Data_out <= stack [read_ptr];
→ finalhaven:可是D out是有條件觸發捏XD
推 espreesso:硬體問題而已..改成if(rst)Data_out<=0;會影響你邏輯嗎?
→ finalhaven:喔喔～這跟=有什麼差別嗎@@"
推 espreesso:FYI  http://0rz.tw/ca3Mw
→ finalhaven:感謝m=_=m