Re: [問題] verilog signed,mag轉換 與加法

[colinshih (Colin Shih)]

※ 引述《Ohwil (竹南之友)》之銘言：
: 知道verilog 2001之後才支援 reg signed, wire signed
: 我有三個需求
: 1. sign+mag 轉 2's complement
: 2. 2's complement 轉sign+mag
: 3. 2's complement 加法
: 可以合成 verilog code
: 想找example code 但是沒找到
: 自己純手動的轉換怕有沒考慮到的case
: 想求助ㄧ下  QQ

 1.  comp_2 = !smag[N-1] ? smag   : ~{1'b0,    smag[N-2:0]}+1'b1;
 2.  smag = !comp_2[N-1] ? comp_2 :  {1'b1, ~comp_2[N-2:0] +1'b1};
 3.  a + b, each defined reg [N-1:0]
 FYI

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推 Ohwil:想問ㄧ下comp_2是wire signed, smag是 wire,這樣assgin ok?
→ colinshih:all are defined as reg type,
→ colinshih:Even defined in yours, it's ok, because there's no
→ colinshih:any logics, which values depend on signed/unsigned
→ colinshih:, e.g., <, > or signed multiplication.
※ 編輯: colinshih       來自: 111.251.194.220      (06/24 04:19)