Re: RE: Syscall contention tests return, userret() bugs/issues.

In article <[e-mail]>,
Matthew Dillon  <[e-mail]> wrote:
> :
> :Why do you keep saying the Intel caches are write-through?  They've
> :been write-back since the Pentium.  See table 9-2 in the same document
> :I cited before.
> :
>     Maybe I'm using the wrong terminology.  What I mean to say is that
>     Intel caches, under most conditions, will flush dirty elements in
>     their caches to main memory very quickly.  i.e. unlike, say, the old 
>     68040 cache which leaves dirty cache lines in the cache almost
>     indefinitely.  The intel caches implement a write ordering constraint
>     and a FIFO to deal with dirty data.
> 
>     Yes, I guess that would be write-back rather then write-through,
>     But not delayed-write.

It is both write-back and delayed-write.  Section 9.10 ("Store
Buffer") describes it:

    IA-32 processors temporarily store each write (store) to memory in
    a store buffer. The store buffer improves processor performance by
    allowing the processor to continue executing instructions without
    having to wait until a write to memory and/or to a cache is
    complete. It also allows writes to be delayed for more efficient
    use of memory-access bus cycles.

Table 9-1 states that the store buffer has 24 entries on the Pentium 4,
and 12 entries on the P6 family.

John
-- 
  John Polstra
  John D. Polstra & Co., Inc.                        Seattle, Washington USA
  "Disappointment is a good sign of basic intelligence."  -- Ch鐷yam Trungpa


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