Re: RE: Syscall contention tests return, userret() bugs/issues.

:>     But not delayed-write.
:
:It is both write-back and delayed-write.  Section 9.10 ("Store
:Buffer") describes it:
:
:    IA-32 processors temporarily store each write (store) to memory in
:    a store buffer. The store buffer improves processor performance by
:    allowing the processor to continue executing instructions without
:    having to wait until a write to memory and/or to a cache is
:    complete. It also allows writes to be delayed for more efficient
:    use of memory-access bus cycles.
:
:Table 9-1 states that the store buffer has 24 entries on the Pentium 4,
:and 12 entries on the P6 family.
:
:John
:-- 
:  John Polstra
:  John D. Polstra & Co., Inc.                        Seattle, Washington USA
:  "Disappointment is a good sign of basic intelligence."  -- Ch鐷yam Trungpa

    Now we are quibbling over terminology.  Intel caches have a write FIFO.
    They are not a full-blown delayed-write caches.  There is a BIG 
    difference.  That is, you can't have an arbitrary amount of dirty data
    sitting in an intel cache.

    This means that a write will be pushed out to main memory in fairly
    short order.  The only way to prevent this from occuring is to saturate
    the memory bus with cache-missed reads.  There is no confusion here, the
    linux folks did a massive amount of testing of this when they were
    trying to decide whether to force a flush after releasing a mutex or
    whether to allow the cpu to flush it out in the background.  Tests
    showed that the cpu would normally flush the data out within a 
    microsecond or two unless code was carefully crafted to saturate the
    memory bus with reads.
    
					-Matt
					Matthew Dillon 
					<[e-mail]>



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