In article <200203311834.g2VIYrt89705@apollo.backplane.com>,
Matthew Dillon <dillon@apollo.backplane.com> wrote:
>
> Now we are quibbling over terminology. Intel caches have a write FIFO.
> They are not a full-blown delayed-write caches. There is a BIG
> difference. That is, you can't have an arbitrary amount of dirty data
> sitting in an intel cache.
There is nothing in the Intel documentation which would support that
statement. The cache is write-back. Nowhere does the documentation
say anything about dirty lines being flushed to memory except when
required by the cache control protocol (which is pretty standard).
> This means that a write will be pushed out to main memory in fairly
> short order.
No, I don't think so. There is no evidence of that in the Intel
docs.
John
--
John Polstra
John D. Polstra & Co., Inc. Seattle, Washington USA
"Disappointment is a good sign of basic intelligence." -- Ch鐷yam Trungpa
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