Jonathan Mini wrote:
> I am obviously thinking about some other SMP implementation, but I have no
> idea which one. Somebody, somewhere, sets the routing of the clock interrupt
> to be delivered in a round-robin fashion, and then multiplies the clock
> frequency by the number of processors. They're really proud of this solution,
> because (they claim) it reduces contentions of clock-triggered events across
> processors.
>
> Maybe it was Sun?
You are an ex-Be-geek. Maybe it was the BeBox and the two
processor PPC603e box from Apple?
From memory, in addition to using MEI instead of MESI cache
coherency because the CPUs were not built for SMP (the MEI
arbitration was done by putting contention hardware in place
of the L2 cache), interrupt routing was hardware round-robin.
8-).
-- Terry
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