Terry Lambert [tlambert2@mindspring.com] wrote :
> Jonathan Mini wrote:
> > Maybe it was Sun?
>
> You are an ex-Be-geek. Maybe it was the BeBox and the two
> processor PPC603e box from Apple?
That crossed my mind first, but Be wired all of the interrupts to CPU 0 all
the time, including the clock interrupt. It uses IPIs to let the other
processors know of events like VM modifications and scheduling excess.
> >From memory, in addition to using MEI instead of MESI cache
> coherency because the CPUs were not built for SMP (the MEI
> arbitration was done by putting contention hardware in place
> of the L2 cache), interrupt routing was hardware round-robin.
>
> 8-).
That is more detail than I know about the PPC-based BeBox. By the time I joined
Be, we had already officially dropped support for them and were an x86 shop.
--
Jonathan Mini <mini@freebsd.org>
http://www.haikugeek.com
"He who is not aware of his ignorance will be only misled by his knowledge."
-- Richard Whatley
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