[情報] VLSI電路設計導論期中試題!!!

[debet (目標ACE級外野手)]

上次發考卷偷抄了下來 希望明年學弟們用的到~~
這是系壘的福利押^0^

95年 杜弘隆 VLSI導論 期中考試題

1.What are the advantages from the monolithic integration of a large mumber
  of function on a single chip? what's Moore's Law?? (15%)

2.Explain the following terms brifly? (15%)
 (1)Full custom design
 (2)Cell-based synthsis
 (3)Y-chart of VLSI design flow

3.For a VLSI design,we need to emphasis the four characteristic namely,
  hierarchy,regularity,modularity and locality,explain them brirfly...(8%)

4.Consider the layout of a CMOS inverter shown in the right figure,sketch
  its cross-section view (7%)

5.Layout design rules implies a set of constraints put on layout to
  accommodate process variation.Point out the three categories of the rule
  as well as their objective. (12%)

6.Explain the following terms (10%)
 (1)Body-effect
 (2)Channel Length Modulation

7.Device scaling(shrinking) means the reduction of the size of MOSFETs and
  there are two types of device scaling,namely Full Scaling and Constant
  Voltage Scaling . Compare the two scaling approaches in terms of power
  density and power dissipation (8%)

8.There are two types for MOSFETs capacitance,one is deviced-related
  capacitance and the other is interconnect capcaitance. Explain the
  deviced-related capacitance in terms of MOSFETs architecture.(10%)

9.In general,we would like to define five parameters for voltage transfer
  curve (VTC).Explain briefly how can we obtain these parameters for
  different inverter structure such as resistive-load inverters,
  depletion-load inverter and CMOS inverter (15%)

越打英文越順手押XD  報告完畢 <(_ _)>

--
球還沒落地就有機會接殺
         奮力擊出就有機會安打
                                     Debet

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推 cenda:當學弟真好!!!!
推 hcynomo:你認為PO這邊 還會是只有系壘的福利嗎 印下來藏起來啦
推 debet:學長　我怕印起來會不見押　囧　反正偷看沒雞雞XDDD
→ Terrysam:謝謝學長...雖然我目前用不到...
推 websterskimo:用掃描的？
推 rickytr:今天電子二第二次小考我也偷偷抄下來了XD
推 h110381:謝囉~~
推 kaiz:哇嗚~~學長們真是大好人阿XD