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25% loads, 10% stores,11% branches, 2% jumps, and 52% ALU instructions For the pipelined design, load take 1 clock cycle when there is no load-use dependence and 2 when there is. Branches take 1 when predicted correctly and 2 when not. Jumps always pay 1 full clock cycle of delay, so their average time is 2 clock cycles. Other instructions take 1 clock cycle. For pipelined execution, assume that half of the load instructions are immediately followed by an instruction that uses the result and that one-quarter of the branches are mispredicted. Ignore any other hazards. 答案給 Pipelined: Average CPI=1+0.5*1+0.25*1+0.02*1=1.77 好像不太對... 我認為是 CPI=1 + 0.25*1/2*1 + 0.11*1/4*1 + 0.02*1 = 1.11 (load use) (branch) (jump) 有高手可以幫我驗證嗎? 謝謝 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.127.208.96 ※ 編輯: yesa315 來自: 140.127.208.96 (10/19 11:59) ※ 編輯: yesa315 來自: 140.127.208.96 (10/19 12:00)
bennylu:你是對的 10/19 15:26
yesa315:3Q 10/19 15:47
opcan:請問為何不是1.5*0.25+0.1+0.52+1.25*0.11+2*0.02=1.1725? 10/19 22:57