→ yesa315:應該是有forwarding 我覺得答案錯了 10/27 13:56
(97交大電子)的題目
Consider the following MIPS code fragment:
LD R1,45(R2)
DADD R7,R1,R5
DSUB R8,R1,R6
OR R9,R5,R1
BNEZ R7,target
DADD R10,R8,R5
XOR R2,R3,R4
(b) for the classical 5-stage MIPS processor,assume a register file that write
in the first half of clock cycle and reads in the second half cycle forwarding
. which of the dependences that you found become hazard and which do not? why?
解答為
from the pipeline above,we can find only 1&2,1&3 occur data hazard.
other data dependences are solve by half-write half-read register file
and "forwarding strategy".Hence,2 stalls may needed for instruction 2,
and as a sequence,no more stall need for instruction 3.
我想問的是
1.
根據題目的題意 是有支援forwarding嗎?
若有的話 1&3 並不會有data hazard的存在吧
(因為LD指令在執行完mem stage時，可將資料forwarding給DSUB的ALU作輸入用
，故DSUB沒有hazard存在)
2.
若沒有支援forwarding，1&2,1&3 occur data hazard是沒錯的。
那為何解答中寫solve by half-write half-read register file
and ""forwarding strategy""...
另一個想法是，要解決1&2,1&3的data hazard是需要將 DADD的ID stage跟DSUB
的IF stage各stall一個clock，外加forwarding才可解決。但題目沒說清楚?
還是根本就是我沒想清楚...
麻煩各位高手指導一下 謝謝!!
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