ADDI r1，r0，#101
ADDI r2，r0，A
Loop:LD r3，0(r2)
ADDI r3，r3，#1
SD r3，0(r2)
ADDI r2，r2，#4
SUBI r1，r1，#1
BNE r1，r0，Loop
Assume that the branch is resolved during the instruction decode stage,
and full register forwarding are implemented.
Assume that all memory reference hit in the cache and TLBs.
the pipeline does not implement any branch prediction mechanism.
How many stall cycle are in one loop iteration including stalls caused
by the branch instruction?
我想問的是 SUBI r1，r1，#1
BNE r1，r0，Loop 這兩指令中 明顯有data hazard存在
題目說有支援forwarding，那不就應該靠forwarding就能解決這邊的data hazard了嗎?
解答卻是說，需要在這兩道指令中再加一個stall才可。
有人能教我一下為什麼這邊還要stall一個clock呢?
(解答這樣說；Since branch decision is resolved during ID stage,a clock stall is
needed between SUBI and BEQ.)
因為我在做其它考古題時，也有遇到類似情形，但如果有支援forwarding下
都是不用再加一個stall的。
例如中央97的一題 or $3，$2，$1
beq $2，$3，loop 顯然也有data hazard存在
但解答是說用forwarding即可解。
難道是有提到branch decision is resolved during ID stage.
那麼即使在有支援forwarding下，還是要stall一個clock??
麻煩各位指導一下，還是我觀念有錯? 謝謝!!
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※ 編輯: lwtistunning 來自: 220.139.133.70 (10/29 19:09)