※ 引述《yesa315 (XD)》之銘言：
: 25% loads, 10% stores,11% branches, 2% jumps, and 52% ALU instructions
: For the pipelined design, load take 1 clock cycle when there is no load-use
: dependence and 2 when there is.
: Branches take 1 when predicted correctly and 2 when not.
: Jumps always pay 1 full clock cycle of delay, so their average time is
: 2 clock cycles. Other instructions take 1 clock cycle.
: For pipelined execution, assume that half of the load instructions are
: immediately followed by an instruction that uses the result and that
: one-quarter of the branches are mispredicted.
: Ignore any other hazards.
: 答案給
: Pipelined: Average CPI=1+0.5*1+0.25*1+0.02*1=1.77
: 好像不太對...
: 我認為是 CPI=1 + 0.25*1/2*1 + 0.11*1/4*1 + 0.02*1 = 1.11
: (load use) (branch) (jump)
你好像 * 錯了 cpi= 1+ 0.125 + 0.0275 +0.02= 1.1725
: 有高手可以幫我驗證嗎?
: 謝謝
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