推 gn00618777:嗯 一看就懂 謝謝 01/18 22:18
推 lovefo:真厲害...我計組這麼爛 都懂了XD 01/18 22:58
※ 引述《gn00618777 (123)》之銘言：
: Suppose we have a processor with base CPI 1.0,assuming all reference hit
: in the primary cache, and a clock reate of 500MHZ. Assume a main memory
: access time of 200ns,including all the miss handing. Suposse the miss
: rate per instruction at the primary cache is 5%. How much faster will
: the machine be if we add a second cache that has a 20ns access time for
: either a bit or a miss and is large enough to reduce the miss rate to
: main memory to 2%.
500MHZ => 2ns and main memory access time => 100 clock cycle
miss rate 5%
在單層的情況下
CPUtime=0.95*(1)+0.05*(1+100)=6clock cycle
但在雙層純牛肉的口感下
CPUtime=0.95*(1)+0.03*(1+10)+0.02*(1+10+100)
=0.95+0.33+2.22=3.5
最後 除去吧 就將...
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我倒是對 32bits physical address & 4-set 這種問題感到厭惡...
可以有神人寫個供略嘛 >___<""
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我絕對不會說 這是我的無名.........
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