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Consider a MIPS processor with an additional floating point unit. Assume functional unit delays in the processor are as follows: memory (2 ns), ALU and adders (2 ns), FPU add (8 ns), FPU multiply (16 ns), register file access (1 ns), and the remaining units (0 ns). Also assume instruction mix as follows: loads (31 %), stores (21%), R-format instructions (27%), branches (5%), jumps (2%), FP adds and subtracts (7%). and FP multiplys and divides (7%). (1) What is the delay in nanosecond to execute a load, store, R-format, branch, jump, FP add/subtract, and FP multiply/divide instruction in a single-cycle MIPS design? (2) What is the averaged delay in nanosecond to execute a load, store, R-format, branch,jump,FP add/subtract, and FP multiply/divide instruction in a multicycle MIPS design? 想請問一下第二小題,我的想法是直接算 8*31%+7*21%+6*27%+5*5%+2*2%+12*7%+20*7%=8ns 但手邊的答案好像是先求得最大clock cycle time=16ns 再算平均CPI=5*31%+4*21%+4*27%+3*5%+3*2%+4*7%+4*7%=4.24 最後平均delay=4.24*16ns=67.84ns 有高手可以幫我解釋一下題意嗎?? 感恩了!! -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.134.213.201
luckysky1:multicycle 每段時間要一樣 02/08 07:58
crazyjoe:multiycle是以unit time最大的當cycle time 02/08 19:57
crazyjoe:再看全部需要幾個cycle,相乘就是 02/08 19:58
luckyburgess:恩恩 我瞭解了 感謝!! 02/09 00:03
t970320:想問一下jump的cpij為什麼是3 不是只有IF嗎? 02/17 16:37