→ ieric:miss penalty is 6+block size in words 這句話不是有說?= = 02/11 10:55
→ gorocky:對喔!!沒看清楚!! 02/11 11:58
→ gorocky:3Q~! 02/11 11:59
→ gorocky:題目應該只要求miss penalty吧?...不太肯定 02/11 12:00
推 willow02:我也覺得是求cache miss penality 就好 02/20 23:45
這一提示有關memory
是97交大資聯 97中央電機 97政大資科 97台科電子 92清大電機
的考題 類似
consider three processors with differenr cache configurations:
cache1:direct-mapped with one-word blocks
cache2:direct-mapped with four-word blocks
cache3:two-way set associative with four blocks
the following miss rates have been measured:
chche1:instruction miss rate is 4%;data miss rate is 6%
chcah2:instruction miss rate is 2%;data miss rate is 4%
chche3:instruction miss rate is 2%;data miss rate is 3%
Aassume the same program with 10000 instructions is executed on these
processors, and one-half of the instructions contain a data reference.
Assume that the cache miss penalty is 6+block size in words.
Auusme the CPI of this workload was measured to be 2.0 for the processor with
cache1.
(a)determine the number of cycles spent on cache miss for each of these
processors,respectively.
我的問題:
就是a小題是要問miss penalty等於多少吧??
我的答案cache1~cache3都是6
因為我想說增加關聯度只會把miss rate降低.而不會去影響 penalty
而會影響miss penalty卻只有add cache(也就是 有多層的cache)
這樣講應該沒錯!!
可是解答卻給
cache miss penalty total miss
cache 1 6+1=7 10000(0.04*7+0.5*0.06*7)=4900
cache 2 6+4=10 10000(0.02*10+0.5*0.04*10)=4000
cache 3 6+4=10 10000(0.02*10+0.5*0.03*10)=3500
這個答案真令我傻眼
想請問各位高手們
為什麼增加 block容量 以及 增加關聯度 反而會影響 miss penalty?
而且都剛好加4
是我沒看到什麼字.還是哪的觀念錯誤
請糾正我吧!!
感恩的心
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