推 soldier723:我之前也PO過一樣的問題 目前正在努力解= =" 03/02 15:30
→ tedmax100:那能給一下 大概解題的方向嗎 計組念的不太熟 03/02 16:22
a processos uses 32-bit virtual address and 32-bit physical address.
Design the TLB and cache systems for this processor with the following
configurations:
The instructions cache is two-way set associarive design using 32-byte line size.
The instruction cache size is 16KB.
The data che is direct-mapped design using 32-byte line size.
The data cache size is 32KB. Both the cache tags use physical address.
The page size used is 16KB.
The ITLB has 32 entries in total using four-way set associative mapping.
The DTLB has 64 entries in total unsing direct-mapping structure.
(a)show the ITLB and instriction cache design.
(b)show the DTLB and data cache design.
(c)show the block diagram of a 5-stage pipelingd processor integrated with
the above designs
能麻煩要怎解這三題??
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※ 編輯: tedmax100 來自: 122.117.206.69 (03/02 13:54)