作者luckyburgess (心安即自在)
看板Grad-ProbAsk
標題[理工] [計組]-記憶體
時間Fri Mar 19 17:01:28 2010
題目:A computer system uses two levels of cache L1 and L2.
Level L1 is accessed in one clock cycle and supplies the
data in case of an L1 hit. For an L1 miss,occurring 3%
of the time, L2 is consulted. An L2 hit incurs a penalty
of 10 clock cycles while an L2 miss implies a 100-cycle
penalty.
(2)If we were to model the two-level cache system as a single
cache, what miss rate and miss penalty should we use?
(L2's local miss rate is 25% 且pipeline CPI with no
cache miss is 1)
手邊的答案是: miss rate = 3% * 25%
= 0.75%
miss penalty=1+10+100
=111clock
問題: 為什麼miss penalty 是111呀??
麻煩幫我解答一下 感謝!!
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推 assassin88:有點怪@@ 03/19 17:24
→ luckyburgess:恩 挺怪的! 03/19 19:59
推 assassin88:請問一下這是哪年哪一間的考題阿?? 03/19 20:24
→ luckyburgess:95台科大電子的計組 03/19 20:45
推 assassin88:我覺得應該是100 cycle說..XD 你呢? 03/19 21:35
→ luckyburgess:我手邊有另一種版本的答案是給110 XD 03/19 22:12
→ whoisfriday:L2 miss要花100搬到L2中，L1要花10在L2 hit並搬到L1中 03/20 12:42
→ whoisfriday:CPU要花1在L1中Hit並拿來用~所以100+10+1=111 03/20 12:43
→ whoisfriday:可以這樣解釋嗎…… 03/20 12:43
推 s0071988js:樓上正解吧,因為HIT就1 失敗從MEM到CPU確實111 09/29 16:25