推 bigrat2:書本也沒有說明..請問你說的傳輸時間是指什麼的傳輸時間？ 03/24 11:23
→ assassin88:就是讀完 data 後傳回去的時間 03/24 11:28
→ assassin88:樓上..why? 03/24 14:39
→ assassin88:推錯= = 03/24 14:40
※ 引述《bigrat2 (MrEric)》之銘言：
: A bus system consists of a multiplexed 32 bit for transferring both
: address and data. There are 1G memory locations and 4I/O modules to be
: referenced by CPU. A centralized arbitration scheme (No hidden arbitration)
: with a clock rate of 40 MHz is used.
: Assuming that
: (1)Memory latency time (the time required to latch the requestd
^^^^^^^^^^^^^^^^^^^(40ns/25ns) => 每次讀memory皆要2cycle
: data on the bus) =40nsec ,and
: (2)Memory word length =4 bytes
^^^^^^^^^^^^^^^^^^^^memory一次讀4byte
: (3)CPU always requests data in a block of 4words, and it takes two bus
: cycles for bus arbitration and one bus cycle for transferring address
^^^^^^^^^^^^^^^2cycle ^^^^^^^^^^^^^^^^^^^^1cycle
: to main memory.
: Calculate the effective bus bandwitdth (in Mbytes/sec) if CPU accesses
: the 4words at the same time in a Block Data Transfer Mode?
^^^^^^access 4words = 16bytes => 4次memory access = 4*2
: 答案
: f=40MHz =25ns
: 傳送4words 需要2+1+4x2+1 =12 clock (想不出來這一部分怎麼求得的）
^^^^^^^^^基本上我認為答案寫到2+1+4*2就差不多了，
我猜測你答案後面的+1應該是transfer time，
因為此題題目內沒有這項資訊~
: 12 clock =300ns
: 所以頻寬＝4x4Byte x 1/300ns =53.3Mbyte/sec
: 麻煩各位高手指點了
: 謝謝大家
希望對你有幫助~
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