[理工] [計組] pipeline

[christianSK (AG)]

(96 中央資工)

There is an unpipelined processor that has a 1 ns clock cycle and that

uses 4 cycles, for ALU and branch operations and 5 cycles for memory

operations. Assume that the relative frequencies of these operations are 40%,

20% and 40% respectively. Suppose that due to clock skew and setup, pipelining

the processor adds 0.2 ns of overhead to the clock. Ignoring any latency impact

how much speedup in the instruction rate will we gain from a pipeline

implementation?

我知道沒有 pipeline的 avg time 是 4.4 ns

我想問的是 : 給了指令混合比例之後, 在pipeline中怎麼算avg time呢?


另外一個問題 (關於harzard)

為了要早些判定 branch 是否會發生 所以我們把branch的判定拉到ID stage

那如果說一個 lw 指令跟其後的 beg 存在 data harzard

ex:    lw $t1 0($t2)

       beg $t1 $t3 somewhere

這樣是否一定要 stall 兩個 clock 來處理 data harzard

而無法用forwarding的方式處理 ?

謝謝!

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