推 christianSK:嗯嗯 謝謝 10/07 22:30
※ 引述《christianSK (AG)》之銘言：
: (96 中央資工)
: There is an unpipelined processor that has a 1 ns clock cycle and that
: uses 4 cycles, for ALU and branch operations and 5 cycles for memory
: operations. Assume that the relative frequencies of these operations are 40%,
: 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining
: the processor adds 0.2 ns of overhead to the clock. Ignoring any latency impact
: how much speedup in the instruction rate will we gain from a pipeline
: implementation?
: 我知道沒有 pipeline的 avg time 是 4.4 ns
^^^^^^^^ 不要用avg time 容易混淆
可以算出multicycle的 avg CPI = 4.4
假設有n個指令
cpu time = 4.4 * n * 1 = 4.4 * n
對pipelined而言 CPI可以視作1
cpu time = 1 * (n+4) * (1+0.2) = 1.2 (n+4)
^^^ 4 = 5-1 這個用時間圖就知道為何了。
4.4 n .
speedup= ------------ === 3.67
1.2 (n+4) .
: 另外一個問題 (關於harzard)
: 為了要早些判定 branch 是否會發生 所以我們把branch的判定拉到ID stage
: 那如果說一個 lw 指令跟其後的 beg 存在 data harzard
: ex: lw $t1 0($t2)
: beg $t1 $t3 somewhere
: 這樣是否一定要 stall 兩個 clock 來處理 data harzard
: 而無法用forwarding的方式處理 ?
: 謝謝!
lw IF ID EXE MEM WB
beg stall stall IF ID EXE MEM WB
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