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題目如下: Given a MIPS instruction sequence shown below . Assume this code is executed on a pipelined MIPS CPU with a five-stage pipeline, full forwarding, and a predict-taken branch predictor. In addition, assume this CPU can finish the register write in the first half cycle and the register read in the second cycle. L3 : add $s6 , $s6 , $s5 addi $s5 , $s5 , 2 slti $t0 , $s5 , 10 bne $t0 , $zero , L3 sw $s6 , 100($gp) (1) Assume the branch is taken , please draw the simple(traditional) multiple-clock-cycle pipeline execution diagram of the first 5 executed instructions, including all necessary stalls. (2) If the branch is not taken, please redraw the simple(traditional) multiple-clock-cycle pipeline execution diagram of the first 5 executed instructions, including all necessary stalls. 請問這兩小題要怎麼寫比較好 ? 題目似乎沒有提到有無將 branch 之決定提前到 ID stage 第一題我的答案是這樣: L3 : add $s6 ,$s6 ,$s5 IF ID EX MEM WB addi$s5 ,$s5 , 2 IF ID EX MEM WB slti$t0 ,$s5 , 10 IF ID EX MEM WB bne $t0 ,$zero , L3 * IF ID EX MEM WB (EX 前饋給ID) add $s6 ,$s6 ,$s5 IF ID EX MEM WB 想了一想前饋不是只有 EX->EX 或是 MEM->EX ? 有 EX->ID 的嗎? 感覺寫錯了 第二題就不會了 beq後面被沖刷部份不會描述 還請各位大大幫忙 謝謝! -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.117.120.229
compulsory:full forwarding => EX->ID是允許的 12/21 23:51
compulsory:不過這樣講好像怪怪的 我想你的意思是EXE做完 到MEM才 12/21 23:56
compulsory:forwarding至ID 12/21 23:57
compulsory:而且好像也是在ID的地方會stall 12/21 23:59
compulsory:不是還沒抓指令就先stall 12/22 00:00
skill91002:c大的意思是要IF * ID EX MEM WB 這個順序嗎? 12/22 10:59