[理工] [計組] 99台聯大電機

[mickeyha (M*schief)]

Assume three 32-bit variables x, y, and z, are stored in memory

with address A, B and C, respectively.

(1)For the "load-store" instruction set architecture processor,

   write down the assembly codes to compute x+y-z and then stores

   the result back to C.

(2)Suppose that all instruction operation codes are 6 bits,

   memory address are 24 bits(byte-addressable),

   and register address are 5 bits.

   What are the code size(in terms of bits) and the total memory access

   (in terms of bytes) for the codes in(1)?

   Note that the total memory access include both instructions and data

   moves to or from memory.

   And, the memory access must be aligned.

我標黃色的地方真的不太會算 >____<

寫出指令還OK

lw  $s1,A
lw  $s2,B
lw  $s3,C
add $t1,$s1,$s2
sub $t2,$t1,$s3
sw  $t2,C

跪求強者解答 ︿(￣︶￣)︿



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Why Not ：-P

http://whynot-p.blogspot.com/


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※ 發信站: 批踢踢實業坊(ptt.cc) 
◆ From: 61.224.51.5
推 kiwidoit:4
→ kiwidoit:3 loadword operations + 1 storeword operations,thus=4
→ mickeyha:感恩:))) 只是我不會算Byte數耶XD 像是第一行
→ mickeyha:答案寫 8+4 =12 byte 請問是為什麼呢
推 kiwidoit:24 address memory bits/8 bits(a byte)=3 byte per
→ kiwidoit:memory access. 4 memory access=3*4=12bytes.