作者mqazz1 (無法顯示)
看板Grad-ProbAsk
標題[理工] [計組] multi-level cache
時間Fri Jul 15 20:29:19 2011
assume that main memory accesses take 70ns and that memory accesses are 30%
of all instructions. the following table shows data for L1 caches attached to
each of two processors, P1 and P2
L1 size L1 miss rate L1 hit time
P1 1 KB 11.4% 0.62ns
P2 2 KB 8.0% 0.66ns
(2) what is the AMAT for P1
0.62 + (11.4% * 70) = 8.6ns
然後還有另一個數據
13.87 cycles 請問這個是怎麼來的?
(3) 這題是P2比較快 為什麼?
謝謝
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◆ From: 61.228.27.152
→ compulsory:(2)8.6ns/0.62ns 07/15 21:42
→ compulsory:(3)P1 13.87*1.3=18.03 07/15 21:42
→ compulsory: 0.66+(8%*70)=6.26 07/15 21:46
→ compulsory: P2 6.26ns/0.66ns=9.48 9.48*1.3=12.32 07/15 21:49
推 compulsory:P1 CPI=18.03 P2 CPI=12.32 在乘clk cycle time 比較 07/15 21:53
推 lexa:請問樓上1.3哪來的? 07/17 02:04
→ compulsory:指令100%+30%記憶體指令 07/17 22:26