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suppose that in 1000 memory references there are 60 misses in the first-level cache, 30 misses in the second-level cache, and 5 misses in the third-level cache. assume the miss penalty from the L3 cache to memory is 100 clock cycle, the hit time of the L3 cache is 10 clocks, the hit time of the L2 cache is 5 clocks, the hit time of L1 is 1 clock cycle, and there are 1.5 memory references per instruction AMAT = 1 + 0.06*5 + 0.03*10 + 0.005*100 = 2.1 clock cycles (4) what is the average stall cycle per instruction (2.1 - 1) * 1.5 = 1.65 clock cycles 請問 -1 是什麼意思? 謝謝 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 61.228.27.152
compulsory:因為是算stall overhead 所以扣去完美CPI 1 07/15 21:40
mqazz1:可否請問為什麼算stall要扣掉完美CPI? 07/16 19:56