cache block size(B) can affect both miss rate and miss latency. Assuming the
following miss rate table, assuming a 1-CPI machine with an average of 1.35
references (both instruction and data) per instruction, find the optimal block
size given the following miss rates for various block sizes
8 16 32 64 128
8% 3% 1.8% 1.5% 2%
(1) what's the optimal block size for a miss latency of 20*B cycles?
(2) what's the optimal block size for a miss latency of 24+B cycles?
張凡下冊182頁
================
Assume a memory system that supports interleaving either four reads or four
writes. Given the following memory addresses in order as they appear on the
memory bus: 3, 9, 17, 2, 51, 37, 13, 4, 8, 41, 67, 10,
which ones will result in a bank conflict?
我的過程
Bank Bank conflict
3 X
1 X
1 O
2 X
3 之後不會
1
1
0
0
1
3
2
請問這要怎麼解?
張凡下冊187頁
謝謝
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 61.228.26.148