推 mqazz1:謝囉! 187頁的題目好奇怪.. 08/20 20:28
→ metalalive:conflict 的發生原因&造成結果 (在下面) 08/24 12:23
→ metalalive:弄懂它的解釋應該就可以解類題了 :P 08/24 12:24
推 brian551a: 第二題有算錯喔 應該是要乘64+24才對 所以答案是32byte 05/20 00:02
→ brian551a: s比較小！ 05/20 00:02
※ 引述《mqazz1 (無法顯示)》之銘言：
:cache block size(B) can affect both miss rate and miss latency. Assuming the
:following miss rate table, assuming a 1-CPI machine with an average of 1.35
: references (both instruction and data) per instruction, find the optimal block
: size given the following miss rates for various block sizes
: 8 16 32 64 128
: 8% 3% 1.8% 1.5% 2%
: (1) what's the optimal block size for a miss latency of 20*B cycles?
找最佳的block size = 找 memory-stall 最少的
block size memory-stall = (miss rate)*(miss penalty)
8 1.35 * 8 % * (20* 8)
16 1.35 * 3 % * (20* 16)
32 1.35 * 1.8% * (20* 32)
64 1.35 * 1.5% * (20* 64)
128 1.35 * 2 % * (20*128)
因為20 , 1.35都是常數看失誤率乘區塊大小 找最小值就好了
所以 .... size rate*size
8 0.64
16 0.48 <--min
32 0.576
64 0.96
128 2.56 因此最佳解 16 byte
: (2) what's the optimal block size for a miss latency of 24+B cycles?
同上題一樣 只是區塊逞罰關係變用加的 一樣找延遲最少
SIZE memory-stall
8 1.35 * 8 % * (24+ 8) = 1.35*8% * 32 = 1.35 * 2.56
16 1.35 * 3 % * (24+ 16) = 1.35*3% * 40 = 1.35 * 1.2
32 1.35 * 1.8% * (24+ 32) = 1.35*1.8%* 56 = 1.35 * 1.008
64 1.35 * 1.5% * (24+ 64) = 1.35*1.5%* 64 = 1.35 * 0.96 <-min
128 1.35 * 2 % * (24+128) = 1.35*2% *152 = 1.35 * 3.xx
因此最佳解 64 byte
對了~ 1.35是因為每個指令平均參考記憶體1.35次
: 張凡下冊182頁
: ================
: Assume a memory system that supports interleaving either four reads or four
: writes. Given the following memory addresses in order as they appear on the
: memory bus: 3, 9, 17, 2, 51, 37, 13, 4, 8, 41, 67, 10,
: which ones will result in a bank conflict?
: 請問這要怎麼解?
: 張凡下冊187頁
: 謝謝
這題我也很好奇要怎麼做XD
以上....有錯誤請幫忙指正 感激不盡
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