推 jim055006:sit是甚麼指令啊?? 10/09 23:08
我寫錯了 是slt才對
※ 編輯: lexa 來自: 27.105.7.134 (10/10 16:13)
Assume the following clock cycle time, ALU latency, and Mux latency
instruction clock cycle time ALU latency Mux latency
a. add $1,$2,$3 100ps 80ps 10ps
b. slt $2,$1,$3 80ps 50ps 20ps
(3)What is the value of the PCsrc signal for this instruction? This signal is
generated early in the MEM stage (only a single AND gate). What would be
a reason in favor of doing this in the EX stage? What is the reason against
doing it in the EX stage?
這題我大概只知道因為不是jump指令所以PCsrc=0
接下來的問題我就不會了...
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