[理工] 計組 99清大資工

[SiriusCloud (古月小楓)]

Assume that a single cycle datapath with the critical path
of 10 ns can be partitioned into arbitary number of balanced
stages for pipelining , and there is no dependency between
instructions .

If the pipeling will introduce an addtional 1 ns delay to
each stage. What is the speed up for the 4-stage pipelined
datapath when compared with the single-cycle one?

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answer :

The instruction time for a single-cycle machine = 10 ns

The instruction time for pipeline = (10 / 4) + 1 = 3.5 ns
                                    ^^^^^^^^^^^^why?

speedup = 10 / 3.5 = 2.86

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◆ From: 219.223.252.31
→ vendor47:題目寫balanced stages，然後是4-stage pipelined
→ vendor47:所以一個stage的時間是(10 / 4)
→ vendor47:第二段寫addtional 1ns delay to each stage，所以 + 1
→ SiriusCloud:可是切4個stage 為什麼不是+4?
→ SiriusCloud:他不是說each 嗎?
→ vendor47:我的想法是，若以instruction數為n，而n很大的話
→ vendor47:single-cycle平均一個instruction的時間為(n*10)/n=10
→ vendor47:pipeline平均instruction的時間為(n+3)*(2.5+1)/n=2.5+1
→ robert527152:就算每個stage+1ns 算pipeline還是只會+1阿@@