[理工] 計組 判斷hazard

[SiriusCloud (古月小楓)]

Given a MIPS instruction sequence shown below.

Assume the code is executed on a five-stage
(IF,ID,EXE,MEM,WB) pipelined MIPS CPU with the
capability to finish the register write in the
first half cycle and the register reads in the
second half cycle


1.sll     $t1,    $s1,2

2.add     $t1,    $s2,$t1

3.lw      $s3,    100($t1)

4.addi    $s3,    $s3,1

5.add     $zero,  $s4,$s3

6.slt     $t2     $s3,$zero

7.bne     $t2,    $zero,L2


----------------------------------
我想問 (1.2)有data hazard , 為什麼(1,3)沒有?

--
※ 發信站: 批踢踢實業坊(ptt.cc) 
◆ From: 219.223.252.31
→ Byzantin:因為有(2,3)
→ RoyalCh:推樓上
推 kimkang:一樓的意思是 只要後面的有hazard 以靠近最近指令的hazard
→ kimkang:為主嗎?
→ metalalive:YES
→ SiriusCloud:感謝^^~