[理工] [計組]multicycle cycle time

[jim055006 (好崩潰)]

Compare the performance for single-cycle, and multicycle control by the average
instruction time using the following instruction frequencies(25% loads, 10%
stores, 11% branches, 2% jumps, and 52% ALU instructions) and functional unit
times(200 ps for memory access, 100 ps for ALU operations, and 50 ps for
register file read or write).

Now the memory access became 2 clock cycle long. Find the relative performance
of the single-cycle and multicycle designs by the average instruction time as
described above.



我的問題是
解答中
multicycle:

load 7 clock
store 6 clock
branch 4 clock
jump 4 clock
ALU 5 clock

cycle time=max{100ps,100ps,50ps,100ps}=100ps
                ﹨    ∕
                 ﹨  ∕
                  200ps


為什麼200ps要被拆成2個100??(想必跟memory access變成2個clock有關)
但是為什麼呢??

有請高手幫解惑!!!
鋼溫!!

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推 cclthomas:題目意思是說  同樣的memory access time變成兩個 clock
→ cclthomas:去完成  所以 clock cycle time 可以被減短
→ jim055006:感謝!!了解了~~