[理工] [計組] CLA delay

[gn123 (GnCtIlike)]

發現學校期中考答案怎好像跟張凡書不太一樣~"~


a. show the delay 4-bit carry-lookahead adder and 4-bit ripple carry adder


b. show the delay 16-bit adder by two-level carry-lookahead scheme
   (assume AND OR XOR gate take one dalay)


                            CLA                          ripple

a答案不是應該是:   2delay(Ci+1)+1delay(gi)            2(Ci+1)*4

       ( Ci+1 = gi + pi*Ci )

b答案不是應該是:  1delay(pi or gi) + 2delay (Gi) + 2dalay(Ci)


(以下是張凡的圖) : (| 是輸入input箭頭 , 而第二個圖是CLA拆開)
                    v


              a0 ~ a15  &  b0 ~ b15
||||||||  ||||||||   | |   | |   | |   | |   ||||||||
vvvvvvvv  vvvvvvvv   v v   v v   v v   v v   vvvvvvvv
--------  --------  ----- ----- ----- -----  --------
|4-bit |  |4-bit |  | + | | + | | + | | + |  | 4-bit|---------------c0
| CLA  |  | CLA  |  ----- ----- ----- -----  | CLA  |        |
--------  --------   |  |  |  |  |  |  |  |  --------        |
    |  |      |  |   v  v  v  v  v  v  v  v      |  |        |
    |  |      |  |  -------------------------    |  |        |
C4  |  |      |  |  |p7 g7 p6 g6 p5 g5 p5 g5|    |  |        |
 <- |  | C3   |  |C2|     2-level gate      | C1 |  |        |
  | |  |  ^   |  | ^-------------------------  ^ |  |        |
  | |  |  |   |  | |                  |    |   | |  |        |
  | v  v  |   v  v |                  v    v   | v  v        |
--------------------------------------------------------     |
|   P3 G3     P2 G2                  P1   G1     P0 G0 |     |
|                   2-level gate                       |------
|                                                      |
--------------------------------------------------------

C1=G0+c0*P0  => 2 delay

G0=g3 +(p3*p2) + (p3*p2*g1) + ....  => 2 delay

gi= ai*bi => 1 delay




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