[理工] [計組] Data hazard

[LUCENE (LUCENE)]

LD     AX,M[100]    ;AX←M[100]
ADD    AX,BX        ;AX←AX+BX      => AX發生RAW, WAW
MOV    CX, 1        ;CX←1
ST     M[100], AX   ;M[100] ← AX   => AX發生RAW; M[100]發生WAR
ST     M[200], BX   ;M[200] ← BX
ADD    CX,M[200]    ;CX←CX+M[200]  => CX發生RAW, WAW;M[200]發生RAW

Suppose the code segment is executed on a pipeline with five
stages: instruction fetch, operand fetch, memory read (assuming no
need to calculate the effective address), ALU operation, and write
back. Hardware will detect any hazard and stall the affected
instruction. Draw a space time diagram to show how the code
segment is executed through this pipeline.

答案在上面 但看不太懂WAW以及WAR的狀況.. 有高手可以解釋一下嗎..
BTW,我知道WAW和WAR的解釋 但在這題上我完全看不懂 = =


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→ martin77:1,2行都寫入AX,3，6行都寫入CX,所以皆有WAW
→ martin77:等等，你是不懂程式碼在作啥，還是?
→ BaaaSwin:LD的目標reg=AX ADD的來源reg=AX.BX--->RAW
→ BaaaSwin:LD的目標reg=AX  ADD的目標=AX-->WAW
→ BaaaSwin:ADD的目標AX  ST的來源AX-->RAW
→ BaaaSwin:依此類推...記憶體位址我就不知道有沒有datadependency了
→ LUCENE:我的疑問是.. 2行會比1行先寫入到AX嗎..
→ LUCENE:不是要到WB階段才會寫入AX嗎? 這樣不就表示1行一定先寫入AX
推 Bearcome:RAW WAW WAR有就行了 不一定要發生危障
→ LUCENE:如果一行會先寫入AX 接著換二行寫入到AX..就沒有WAW hazard
→ LUCENE:喔喔 了解
推 Bearcome:以MIPS來說就只有WAR會發生危障 同樣意思
→ Bearcome:                RAW 抱歉
→ LUCENE:但是有RAW WAW WAR不就代表有data hazard?
推 Bearcome:要視指令級架構而定喔
→ LUCENE:所以你的意思說這一題沒有WAW hazard嗎?
→ LUCENE:此題第一小題是Identify all possible RAW,WAR,WAW hazard.
→ BaaaSwin:WAW不是hazard是dapadependency!只有RAW才有可能發生
→ BaaaSwin:hazard