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[kiwidoit (伊佛利特)]

5 stage pipeline:

IF  ID  EXE  MEM  WB

We have the following functional unit times:
(1) 200ps for memory access
(2) 100ps for ALU operation
(3) 50ps for register file read or write
and the following instruction frequencies:
(4)25% loads
(5)10% stores
(6)11% branches
(7)2% jumps
(8)52% ALU operations

Now suppose the memory access became 2 clock cycles long.

下面是修改後新的pipeline stage

IF1  IF2  ID  EXE  MEM1  MEM2  WB

For branches assume that one-quarter of the branches are misspredicted(delay
2 cycles if misprediction).

For loads, assume that the subsequent instructions depend on the load with
a probability of 1/2, 1/4, 1/8, 1/16, and so on. That is, the instruction
following a load by two has a 25% probability of using the load result as
one of its sources.

Ignoring any other data hazards, find the Average instruction time.

這邊解答給 effective CPI for loads is 0.5*3 + 0.125*2 + 0.375*1 = 2.125
為什麼不是0.5*3 + 0.25*3(多加這一項) + 0.125*2 + 0.125*1 @@?

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