推 banjmin:12只是說cycle time影響的是stage的delay time 跟throughp 10/22 07:38
→ banjmin:ut沒直接關係 10/22 07:38
推 banjmin:3 4都後半段錯吧 10/22 07:43
如果有張凡課本可直接參考上冊P437.P438的練習題
題目:A group of students have been debating the efficiency of five-stage pipeline when one student pointed out that not all instructions are active in every stage of the pipeline.After deciding to ignore the effects of hazards,they made the following five statements.Which ones are correct?
1.Allowing jumps,branches,and ALU instructions to take fewer stages than the five required by the load instruction will increase pipeline performance under all circumstances.
2.Trying to allow some instructions to take fewer cycles does ont help,since the throughput is determined by the clock cycle;the number of pipe stages per instruction affects latency,not throughput.
3.Allowing jumps,branches,and ALU operations to take fewer cycles only helps when no loads or stores are in the pipeline,so the benefits are small.
4.You cannot make ALU instructions take fewer cycles because of the write-back of the result,but there is some opportunity for improvement.
5.Instead of trying to make instructions take fewer cycles,we should explore making the pipeline longer,so that instructions take more cycles,but the cycles are shorter.This could improve performance.
ANS:2 and 5 are correct
我的想法:
1.2講的應該是同一件事，都是說某些指令減少stages只會影響latency而不是throughput?
3的話不太懂是什麼意思，麻煩大家給我一點想法了
4的話我覺得是不是branches跟jump不能使用更少的cycles(一定要用到IF.ID.EXE這三個)?
所以4的話是錯的? 是錯在這部分嗎?
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