看板 ICDESIGN 關於我們 聯絡資訊
有人遇到跟我一樣的問題嘛? debussy打不開~~ 視窗顯示訊息: Compiling source file "lib.v" Compiling source file "testbench_mac2x2.v" Compiling source file "mac2x2.v" Error! Module (test) has a `timescale directive but previous modules do not [Verilog-MODTDN] "testbench_mac2x2.v", 9: module test; 1 error End of Tool: VERILOG-XL 05.30.002-s Jan 3, 2006 21:33:12 cad32:/home/raid1_3/user93/r3942123/test% source /usr/debussy/cshrc platform=SOLARIS2 cad32:/home/raid1_3/user93/r3942123/test% debussy& [1] 29559 cad32:/home/raid1_3/user93/r3942123/test% logDir = /home/raid1_3/user93/r3942123/test/debussyLog Debussy - The Knowledge-Based Debugging System, Release 5.4v6 (SOLARIS/64bit) 12/02/2004 Copyright (C) 1996 - 2004 by Novas Software, Inc. rcfile = /usr/debussy/etc/novas.rc Error: Can't open display: -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.42.22
ALEXXXX:setenv DISPLAY localhost:XX XX是你的putty設定的 01/03 22:01
ErnestK:請試試下一篇的方法 01/03 22:04