嗯~我想問的重點是最後ㄧ行:(
針對剛剛.v檔順序我重新KEY IN了..所以這次run沒有上ㄧ篇那個問題
Compiling source file "testbench_mac2x2.v"
Compiling source file "lib.v"
Compiling source file "mac2x2.v"
Highest level modules:
test
HA1
IV
ND2
Novas FSDB Dumper for Verilog-XL, Release 5.4v6 (SOLARIS) 11/30/2004
Copyright (C) 1996 - 2004 by Novas Software, Inc.
*Novas* Create FSDB file 'mac2x2.fsdb'
*Novas* Start dumping the top scope(test), layer(0).
*Novas* Start dumping the top scope(HA1), layer(0).
*Novas* Start dumping the top scope(IV), layer(0).
*Novas* Start dumping the top scope(ND2), layer(0).
*Novas* End of dumping.
Verification failed.
L91 "testbench_mac2x2.v": $finish at simulation time 19824
0 simulation events (use +profile or +listcounts option to count) + 175 accelerated events
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool: VERILOG-XL 05.30.002-s Jan 3, 2006 21:49:57
cad32:/home/raid1_3/user93/r3942123/test% source /usr/debussy/cshrc
platform=SOLARIS2
cad32:/home/raid1_3/user93/r3942123/test% debussy&
[1] 29610
cad32:/home/raid1_3/user93/r3942123/test% logDir = /home/raid1_3/user93/r3942123/test/debussyLog
Debussy - The Knowledge-Based Debugging System, Release 5.4v6 (SOLARIS/64bit) 12/02/2004
Copyright (C) 1996 - 2004 by Novas Software, Inc.
rcfile = /usr/debussy/etc/novas.rc
Error: Can't open display:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
打不開debussy呀~~~~~~~~~~~
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※ 編輯: Sharon9 來自: 140.112.42.22 (01/03 22:17)