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課程名稱︰類比積體電路設計
課程性質︰系訂選修
課程教師︰劉深淵
開課學院：電資學院
開課系所︰電機系
考試日期（年月日）︰2009.4.14
考試時限（分鐘）：120
是否需發放獎勵金：是，謝謝
（如未明確表示，則不予發放）
試題 :
1. Describe the basic processing steps to realize the CMOS devices(10%).
2. To realize an NMOS device, two of the steps are realizing n+ regions
(drain or sources for an NMOS device) and realizing its poly gate.
Which step should be performed first? Why? (5%)
(原題目有誤,上述為老師修改過後的題目)
3.(a) Draw a cross section of an NMOS with p-substrate (5%).
(b) Describe all the parasitic capacitances for (a) in triode region and
saturaion regions. (10%)
(c) Plot the small-signal model of an NMOS including the parasitic
capacitance. (10%)
(d) Describe the second-order effects for a MOS device. (10%)
(e) Describe three layout schemes to match two wide-width devices. (5%)
(f) Plot the layout of two matched capacitors with the ratio of 1:8. (5%)
(g) Describe what is the CMRR and its definition. (5%)
4.(a) Calculate the transfer function of Fig.1(a) by using Fig.1(b). (10%)
(b) Calculate the input impedance of Fig.1(a) from the node X to the right
direction. (10%)
(註:本題圖請參考課本P.178 Fig 6.17)
5.(a) Calculate the transfer function by using the simplified high-frequency
model of the differential pair in Fig.2. (5%) (assume ro3>>1/gm3, and
ro1 = ro2)
(b) If the current mirror pole is much higher than the output pole, please
calculate the poles from (a). (10%)
(註:本題圖請參考課本P.191 Fig.6.31(a))
課本: Behzad Razavi, "Design of Analog CMOS Integrated Circuits"
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