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推 gsiplo:謝囉 雖然看不懂 10/17 20:44
作者 w86083 (可樂果) 看板 backbrain
標題 [電子]
時間 Fri Oct 7 12:10:46 2011
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已經經過電路板測試
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Name Gates;
Partno CA0001;
Revision 04;
Date 9/12/89;
Designer G. Woolhiser;
Company Logical Devices, Inc.;
Location None;
Assembly None;
Device g16v8a;
/****************************************************************/
/* */
/* This is a example to demonstrate how CUPL */
/* compiles simple gates. */
/* */
/****************************************************************/
/*
* Inputs: define inputs to build simple gates from
*/
Pin 1 = a;
Pin 2 = b;
Pin 3 = c;
/*
* Outputs: define outputs as active HI levels
*
*/
Pin 12 = A;
Pin 13 = B;
Pin 14 = C;
Pin 15 = D;
Pin 16 = E;
Pin 17 = F;
Pin 18 = G;
/*
* Logic: examples of simple gates expressed in CUPL
*/
A=((a & c)# (!a & !c)) # b;
B=((a & b) # (!a & !b))# !c;
C=(((!c & !b) # a) # c);
D=(!a & !c) # (!a & b) # (b & !c) # ((c & a)& !b);
E=((!c & !a) # (!a & b));
F=((!a & !b) # c);
G=(((!c & b) # (!a & b)) # (!b & c));
inva = !a; /* inverters */
invb = !b;
and = a & b; /* and gate */
nand = !(a & b); /* nand gate */
or = a # b; /* or gate */
nor = !(a # b); /* nor gate */
xor = a $ b; /* exclusive or gate */
xnor = !(a $ b); /* exclusive nor gate */
--
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