This paper proposes a grid-based congestion estimation (GBCE)
algorithm to estimate the congestion and choose the suitable
circuit structure at the synthesis stage. The GBCE algorithm
can be divided into three parts: cell placement algorithm,
wire estimation algorithm, and reconstruction and re-synthesis
algorithm.
The cell placement algorithm uses Equation (1) to get the cell
location of LC. However, how does the algorithm get the
location of LC when P_set is empty?
We expect that more experiments with different designs are
performed in your experimental result. More results with different
designs can prove that your method is not just suitable for a
special design. Besides, we do not see any comparison with
previous works [6, 7, 8]. Finally, Physical Compiler can be run
on several modes: timing, power, area, and congestion. Do you run
Physical Compiler on congestion mode in Table 2?
The structure of content is disorderly. For example, experimental
results embed in Section III. Besides, please check your paper
carefully, since there are many typos in your paper. For example,
"GB[W]E" in Section I, "Design [Compiler]" in Section II.D,
"Physical [Compiler]" in Section III, "All of the synthesized
netlist [are] placed..." in Section III, and "according [to]"
in all sections.
※ 編輯: bluetai 來自: 140.112.233.88 (05/28 07:06)
※ 編輯: bluetai 來自: 140.112.233.88 (05/28 15:03)