[雜事]my review comment

[internal (水)]

大家如果有空 也看看吧
Repeaters are used to reduce the delay on global wires.
As feature size scaling down, we need more repeaters to meet the timing
requirement. Such huge number of repeaters will occupy a lot of routing
resources and make the routing more difficult.

This paper proposes a way to reduce the count of repeaters by minimizing
the number of global nets. The technique is to add an on-line wirelength
estimation, and use this information to guide the top-down placement.
This concept is simple but it has a good result on reducing global nets.

However, several points need to be taken care of:
1: CL (critical wirelength) is assumed to be 20%, 30%, 40% of the
   chip's half perimeter. A more realistic calculation of CL
   (ex: using the parameters of certain technology) can give us a better
   insight into this problem.
2: LBB and MLBB are little used to estimate the wirelength, and the
   results are much worse than CBB and MCBB. Why the author spent a lot
   of time to compare the results between LBB (LBB) with CBB (MCBB)?
3: In table 2 and 3, the term “HPWL” and “WireLength” are a little
   vague. One may consider them to be total wirelength, while another may
   think it as the sum of wirelength of the wires longer than CL.
   The term “# Nets” also needs more explicit explanation.
4: In page 4, the author claims that a larger alpha tends to increase
   the total wirelength. We look forward to more explanation about it.
5: Formula 2 in page4:
                “W”CBB->”M”CBB

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推 yellowfishie:第八行不用加逗號 estimation" "and use..
推 yellowfishie:2. Why "does" the author "spend" a lot..
推 yellowfishie:the results between LBB (LBB) "and" CBB
推 bluetai:第一行: As feature size "scales" down
→ bluetai:sorry~ 第二行~ :p
推 bluetai:倒數第八行: In table"s" 2 and 3
→ bluetai:同一行: the term"s"...
推 bluetai:建議: 一般來說,我會用authors而不用the author.