Re: 暑假 DAC paper報告

[bluetai (夏日香氣--孫藝珍)]

tchsu:  35.2 Timing-Driven Placement by Grid-Warping
        35.3 Faster and Better Global Placement by a
             New Transportation Algorithm

elephant:  Path Based Buffer Insertion
           Net Weighting to Reduce Repeater Counts during Placement

Jiawei:
    12.2 Navigating Registers in Placement for Clock Network Minimization
    34.2 A Low-Latency Router Supporting Adaptivity for On-Chip Interconnects

Annika:
        23.1 Design Methodology for IC Manufacturability Based
             on Regular Logic-Bricks
        23.2 Advanced Timing Analysis Based on PostOPC Extraction
             of Critical Dimensions
waves:
        19.2 Robust Gate Sizing by Geometric Programming
        19.3 Circuit Optimization using Statistical Static Timing Analysis


bluetai:
   23.4 RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations

--

--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.112.48.60
※ 編輯: bluetai         來自: 140.112.48.60        (07/06 15:15)