※ 引述《bluetai (夏日香氣--孫藝珍)》之銘言：
tchsu: 35.2 Timing-Driven Placement by Grid-Warping
35.3 Faster and Better Global Placement by a
New Transportation Algorithm
elephant: 30.3 Path Based Buffer Insertion
30.2 Net Weighting to Reduce Repeater Counts during Placement
Jiawei:
12.2 Navigating Registers in Placement for Clock Network Minimization
34.2 A Low-Latency Router Supporting Adaptivity for On-Chip Interconnects
Annika:
23.1 Design Methodology for IC Manufacturability Based
on Regular Logic-Bricks
23.2 Advanced Timing Analysis Based on PostOPC Extraction
of Critical Dimensions
waves:
19.2 Robust Gate Sizing by Geometric Programming
19.3 Circuit Optimization using Statistical Static Timing Analysis
bluetai:
23.4 RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations
fish:
30.1 Power Optimal Dual-Vdd Buffered Tree Considering Buffer Stations
and Blockages
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◆ From: 140.112.25.218
※ 編輯: yellowfishie 來自: 140.112.25.218 (07/08 16:42)