看板 NTUGIEE_EDA 關於我們 聯絡資訊
※ 引述《internal ()》之銘言: ※ 引述《Jarwai (冷淡看一切...)》之銘言: ※ 引述《nextme (^^ 嘿嘿嘿)》之銘言: : ※ 引述《Donnie ( XD)》之銘言: : ※ 引述《enorm (give and believe)》之銘言: : 大家自己列上來吧 : meifc: Improving Single-Pass Redundancy Addition and Removal wi : enorm: (志願1) Formal Presentation of Two Initial Variable Ordering : (志願2) A Novel Heuristic for Constructing Hexagonal Steiner : Trees for Routing in VLSI : jinli or hyliu: A Linear Time Complexity Current Path Analysis : Algorithm for ESD Protection : nextme: : 1. A Partition-Based Voltage Scaling Algorithm Using Dual Supply : Voltages for Low Power Designs : 2. Improving Single-Pass Redundancy Addition and Removal with : Inconsistent Assignments : 3. Gain-based Cell Delay Modeling : 4. Fast and Accurate Peak Power Estimation Through Mixed-Level : Delay Calibration Jiawei: Design Migration from Peripheral ASIC Design to Aera-IO Flip-Chip Design by Chip I/O Planning and Legalization internal gain-based cell delay modeling indark: 1. Investigation of dynamic power consumption reduction in FPGAs 2. Multilevel Large-Scale Modules Placement with Refined Neighborhood Exchange 3. Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization 好像搶到婉萍的志願了 sorry~~ -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.48.60
Jarwai:我要11月23號報告...因為30號我要OR期中考... Orz 11/14 15:16
-- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.48.60 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.4.242