bluetai:
unisun:
athena:
crazying:
donnie:
gwliao:
nextme: 1. A Partition-Based Voltage Scaling Algorithm
Using Dual Supply Voltages for Low Power Designs
2. ??????
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Jiawei: Design Migration from Peripheral ASIC Design
to Aera-IO Flip-Chip Design by Chip I/O Planning
and Legalization
waves: The Fast and Accurate Worst-Case Determination
with Maximum Probability
fish: ??????
mark: ??????
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meifc: Improving Single-Pass Redundancy Addition and Removal
internal: gain-based cell delay modeling
Tien-Chang Hsu
1. Multilevel Large-Scale Modules Placement
with Refined Neighborhood Exchange
2. Design Migration from Peripheral ASIC
Design to Aera-IO Flip-Chip Design
by Chip I/O Planning and Legalization
anna: Speeding Up Static Timing Analysis With Crosstalk:
Discrete Coupling Model Centric Approach
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enorm: (志願1) Formal Presentation of Two Initial Variable Ordering
(志願2) A Novel Heuristic for Constructing Hexagonal Steiner
Trees for Routing in VLSI
indark:
1. Investigation of dynamic power consumption
reduction in FPGAs
2. Multilevel Large-Scale Modules Placement with
Refined Neighborhood Exchange
3. Design Migration from Peripheral ASIC Design to
Area-IO Flip-Chip Design by Chip I/O Planning and Legalization
Akilae: (你選到老闆指定給planet的了, 再挑一篇吧 XD)
jinli or hyliu(??): A Linear Time Complexity Current Path Analysis
Algorithm for ESD Protection
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※ 編輯: Donnie 來自: 140.112.25.204 (11/14 22:55)