推 Donnie:感覺好競爭... T_T 12/11 12:16
推 yellowfishie:多轉一些吧 ^^ 12/11 15:17
→ gwliao:這表示有人認為P&R有出tool的利基. 12/11 20:45
http://www.edn.com/article/CA6510888.html?nid=3351&rid=98718402
EDA place-and-route startup ATopTech out of the gates with Broadcom win
By Michael Santarini, Senior Editor -- EDN, 12/10/2007
Roughly every four years, the EDA industry seems to deal the IC design
community a new batch of place-and-route startups. Like clockwork, a new
group is popping up now, and one of them—a not so stealthy implementation
startup called ATopTech—wants to be the top of the class.
The company was founded in 2003 by a group of P&R developers with an
impressive track record. The company’s lead executives include co-founders
Don-Min Tsou, PhD, president of ATopTech, and Kaiwin Lee, CEO; well-noted
architect Ping-San Tzeng; Eric Thune, VP of sales and marketing; and Eddie
Araki, president of ATopTech KK in Japan. Many members of the ATopTech staff
were former Avanti employees and were crucial to the development of that
company’s Apollo and Astro place-and-route tools. Tzeng was the tool’s
architect and went to Synopsys after it acquired Avanti and served as
Synopsys fellow, before moving over to ATopTech to try to do it once more,
create a leading edge place and route tool.
ATopTech’s Thune said the company quietly released the first version of its
Aprisa floorplanning-to-GDSII system back in 2006 to early customers to get
it ready for mass release. Thune said the tool suite is now ready for
primetime and the company is launching Aprisa concurrently with a big win:
Broadcom.
Rumors had been flying in the IC design community that Broadcom was
evaluating new place and route systems, but which EDA company Broadcom
finally picked remained elusive—at least until now.
Thune would not give nitty-gritty details of the agreement, but said Broadcom
made a “very substantial” multimillion dollar, multi-year licensing deal
with ATopTech. However, Thune agreed that it is not entirely replacing the
incumbent implementation tool, which sources say is Magma. ATopTech claims to
already have 5-plus tapeouts at 90 nm and 65 nm with several 45-nm designs
under way, and counts Raza Microelectronics, in addition to Broadcom, among
its early customers.
Thune claims that while in recent years the larger EDA vendors have been
preoccupied with integrating DFM technologies into their flows, they have not
been paying enough attention to their place and route tools and the problems
their customers in P&R face.
“A lot of P&R tools broke at 65 nm,” said Thune. “They broke for a lot of
reasons but one of the core reasons is we have lots of new challenges, such
as OCV [on chip variation], MCMM [multi-corner multi-mode] issues, as well as
exponential growth of design rules,” said Thune. “As a result of this, run
time has exploded and designs are coming out that are not DRC [Design Rule
Check] clean and are not fixable. And certainly one of the biggest issues we
see is that timing doesn’t correlate to signoff tools. A legacy place and
route tool may tell you it meets timing but when you get the design to
signoff, engineers commonly find there are hundreds and thousands of
violations that need to be fixed manually. As a result of all these, many
design projects slip their schedules—not by a little, but by a lot.”
Thune said that a big problem considering the bulk of design groups haven’t
moved to 65 nm, yet. “Big EDA vendors are sending patches to update their
tools for 65 nm, but users don’t want a tool that goes back and fixes
problems after the place and route tools make them, they want a P&R system
that doesn’t create problems in the first place.”
With these problems in mind, ATopTech architects crafted a new system from
scratch. The Aprisa system includes a floorplanner, placement tool, clock
tree synthesis tool, global router and a detailed router, all using internal
timing analysis and extraction engines.
Thune said the first step ATopTech architects took in creating the suite, was
build Aprisa to take advantage of workstations using multi-core processors.
Thune said the tool can handle more than 2 million instances, claiming a
customer just finished a design that was 4 million instances flat. While the
tool can handle designs that large, Thune said it maintains a reasonably
small memory footprint.
The tool was also built around a proprietary database, rather than using Si2’
s Open Access. Most startups in the implementation space today build their
tools to use the OA common database to more freely interface to third party
tools. But Thune said ATopTech went with a proprietary database rather than
OA to highly tune runtime performance and tool interaction within Aprisa. “
With the design’s we’re talking about, transferring files to an external
database would just slow things down tremendously,” he said, noting the tool
supports the typical formats such as LEF, DEF, .lib and SDF so if users for
example want to use another floorplanner with suite, they can do so.
According to Thune, ATopTech architects also built into the tool native
support for on-chip variation, multi-corner multi-mode design, multi-Vdd and
voltage islands, all of which are commonly applied in advanced designs.
Aprisa, he said, also natively supports DFM requirements and implements
features such as double vias, wire spreading, end of line, and min edge.
“All of these new designs are low power designs so things like multi-Vdd and
voltage islands need to be handled very smoothly in the design flow,” Thune
said. “If you look at legacy tools, designers actually are forced to create
levels of hierarchy to support these—it’s very painful. We’ve made it easy
to implement.”
But the key technology of the Aprisa system is what ATopTech calls its
Interconnect Centric Precision Optimization. “A lot of tools today use
margin-based over optimization to compensate for 65-nm challenges,” said
Thune. “The cause of that is that most of the physical optimization done in
tools today is based on estimated parastics. The result is a lot of the fills
get oversized to try to prevent signal integrity problems up front, but the
penalty for this is you run into much longer run times, much larger cell
counts and higher power usage.”
Thune said ICPO runs throughout the Aprisa flow. “We’re doing it during
placement, clock-tree synthesis, global route and detailed route,” he said.
“The optimization is based on much more precise parasitic and signal
integrity information, and we average parasitic in the placement phase so we
don’t do this over optimization up front.” Thune said the tool includes a
2.5-D extraction engine that provides the data for ICPO.
Another key feature of the tool is its speedy internal timing engine. Thune
said the tool can run approximately a million instances in 5 minutes, boosted
in part by the parallel CPU architecture, and that the tool reads Synopsys
Design Constraint timing files natively and has good correlation to both
Synopsys’ Primetime and Cadence’s CeltIC signoff timers (the tool has two
modes to run with either signoff timer).
Aprisa’s architects also tailored the tool to support MCMM and OCV analysis.
For example, the tool doesn’t require designers use pruning or fan in cones
for OCV analysis. It also has features for control of clock reconvergence
pessimism removal (CRPR) and transition matching for removing common point
pessimism.
In terms of the main tools in Aprisa, ATopTech’s floorplanner reads in DEF
files or designers can use design parameters. The tool supports channeled,
channel-less, and mixed designs, and can implement rectilinear floorplans.
Next is Aprisa’s joint placement and optimization tool. Thune said Aprisa
uses a timing driven analytical placer that is in constant contact with the
tool’s built-in timing engine.
“We’re constantly iterating between wire length, congestion and timing
optimization to come up with the best results,” he said. The tool also
natively supports high fan-out synthesis to ensure it places the optimal
amount of buffers.
Aprisa’s clock-tree synthesis tool supports cluster based clock trees or
meshes, and gated or board generated clocks. The tool can synchronize
generated clock pins, perform automatic clock-gate cloning and de-cloning,
and match latency targets specified by users for any pins. “We believe other
vendors have very weak clock-tree synthesis tools so we put a lot of time
into developing this one,” said Thune.
Thune claimed one big difference between Aprisa and other tools in the
industry, is that Aprisa does global routing and track assignment in a single
step. The tool has a fast algorithm that allows it to handle 2.8 million
instances in roughly 30 minutes. “By doing these together, the global route
is very close in parasitic and SI accuracy to the detailed route,” he said.
In this step, users will iterate between routing and optimization, performing
sizing, buffering and spreading wires guided by SI and timing analysis. Thune
noted the tool will also optimize for MCMM.
The last tool in the Aprisa line up is the company’s hybrid detailed router.
Thune said the company calls it a “hybrid” because it is primarily a
grid-based router, but allows users to route off grid, too. According to the
executive, the tool’s architects spent a great deal of time optimizing the
performance of the router so that it can route 250,000 instances in 5 minutes
running on 8 CPU (Running the tool on 8 CPUs allows the tool to run routing 7
times faster). The tool supports 90-nm/65-nm/45-nm design rules and allows
designers to implement custom rules for wide width spacing, shielding and via
doubling. Like the other tools it is closely linked with the global router,
SI and timing engines and supports MCMM. “We’re doing this all in route
versus doing it as a post processing step,” said Thune.
ATopTech’s Aprisa starts at $750,000 for a one year subscription. The
company is headquartered in Santa Clara, Calif., and currently has 40
employees. The company has raised $14 million in two rounds of venture
capital from Founders, Acorn Campus, H&Q, and Dragon Fund. Thune would not
speculate on the company’s future, but said it is following the lead of
successful EDA startup Apache Design, meaning the company is focused on
putting the technology first and letting the rest of the cards fall where
they may.
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※ 編輯: bluetai 來自: 220.128.66.129 (12/11 10:33)