[EEtimes] TSMC rolls 40-nm design flow

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TSMC rolls 40-nm design flow

Mark LaPedus
EE Times (06/03/2008 12:01 H EDT)


SAN JOSE, Calif. — Paving the way for next-generation chips, Taiwan
Semiconductor Manufacturing Co. Ltd. (TSMC) today will roll out its latest
design methodology for IC production at the 40-nanometer node.
TSMC's Reference Flow 9.0 is a collection of EDA, DFM and other design tools
that will help enable chip designs for its new 40-nm foundry process. The
flow includes support for a second EDA power standard, enhanced statistical
timing analysis and new hierarchical design-for-manufacturing (DFM)
capabilities.


At that node, it also narrows the roster of the company's list of tool
vendors to Cadence, Synopsys, Magma, Mentor, Apache, Extreme-DA, CLK DA and
Azuro.

In 9.0, TSMC now supports the industry-standard Unified Power Format (UPF)
language, which is backed by Synopsys, Mentor, and Magma. UPF supports
integrated low power design flows from RTL to silicon.


Last year, TSMC unveiled its design methodology for IC production at the
challenging 45-nm node, dubbed Reference Flow 8.0. The suite gave a ringing
endorsement to Cadence Design Systems Inc.'s rival low-power EDA standard,
dubbed the Common Power Format (CPF). Reference Flow 9.0 supports both CPF
and UPF.


TSMC has moved into production at both the 45- and 40-nm nodes. In March,
TSMC unveiled its 40-nm process. The process is an interim, "half node" step
toward the 32-nm process node, which TSMC expects to ramp starting late next
year.

Over the years, TSMC has rolled out reference flows at the various process
nodes to help customers reduce their product development times. As part of
those efforts, the company has also offered limited design services and
developed its own physical-layer intellectual property (IP).


In April, the world's largest silicon foundry also unveiled a new and
possibly controversial strategy that involves more collaboration in the early
stages of the IC design process. The so-called Open Innovation Platform (OIP)
consists of a suite of design tools and IP to help customers with their DFM
efforts.


But it could also possibly cause a major stir in the industry, as the silicon
foundry giant wants more of the IC pie and appears to be encroaching on the
turf of the third-party EDA, IP, packaging and test communities.


Officials from TSMC insisted that OIP is not a competitive offering. OIP
helps customers "design and innovate faster," said Tom Quan, deputy director
of design services marketing at TSMC (Hsinchu, Taiwan).

OIP enables TSMC and customers "to collaborate better" in terms of having the
right pieces--such as EDA tools, intellectual-property (IP) and process
platforms--in place, Quan said.


Like before, TSMC is only providing limited IC design service capabilities.
The company provides "very backend stuff" in terms of IC design, but "we are
not doing designs for customers," he told EE Times.


The real goal for TSMC is simple. "We want to collaborate much deeper with
our ecosystem partners," he added.


Hoping to provide more collaboration, TSMC rolled out Reference Flow 9.0. The
flow provides a reference of qualified design tools and flows that give
designers a proven path from specification to tape-out.


There are similarities between Reference Flow 8.0 and 9.0. Reference Flow 9.0
also includes a number of power reduction techniques, including TSMC's clock
gating design flow for dynamic power reduction. The new low-power clock tree
synthesis supports multi-mode/multi-corner, and on-chip variation to reduce
active and leakage power.


Reference Flow 9.0 now supports stage-based on-chip variation, as well as
design-specific on-chip variation derived from statistical analysis. In
addition, new transistor-level path-based statistical static timing analysis
(SSTA) is introduced to enhance timing accuracy and reduce the need for
pre-characterized cell libraries.


Reference Flow 9.0 provides improvements in DFM. It is said to speed up DFM
analysis for large designs and address potential parametric performance
shifts caused by DFM effects.

It also supports the following third-party EDA vendors and tool:


Cadence: Full tool suite, RTL Compiler, SoC Encounter, QRC extraction, ETS,
         VoltageStorm, Encounter test, and DFM tools.

Synopsys: Full tool suite, Design/Power/IC compilers, DFT, PrimeTime,
          PrimeRail, Star-RCXT, Hercules, and PrimeYield DFM tools.

Magma: Full tool suite, Talus system, Quartz SSTA, Quartz DFM, Quartz DRC/LVS.

Mentor: Full physical verification and DFM tool suite, Calibre, Calibre xRC,
        Calibre nmLVS, Calibre LFD, Calibre CMP Analyzer, Calibre Yield
        Analyzer, and DFT & ATPG tools.

Apache: RedHawk, RedHawk-ALP, Sentinel-SSO.

Extreme-DA: GoldTime STA and SSTA

CLK DA: AmberFX TSSTA

Azuro: Power Centric CTS

http://www.eetimes.com/news/design/showArticle.jhtml?articleID=208401660

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