[研究] Double Patterning Makes a Big Debut in Roadmap

[yellowfishie (喵喵喵喵~~~)]

Double Patterning Makes a Big Debut in Roadmap

Aaron Hand, -- Semiconductor International,
2/1/2007

Given that this is an update year rather than a year for a new edition of the
International Technology Roadmap for Semiconductors (ITRS), one wouldn't
necessarily expect to see a lot of major changes. But the 2006 update of the
Lithography chapter has the effects of one significant change written all
over its pages, and that's the introduction of double patterning as a
potential solution for furthering the resolution capabilities of 193 nm
immersion lithography (193i). A possibility that has come on like gangbusters
in the past year (see “Double Patterning Wrings More From Immersion
Lithography ”), double patterning makes an appearance throughout the updated
chapter — within Difficult Challenges, Technology Requirements, and
Potential Solutions.

The ITRS's Lithography technology working group (TWG) has deemed it
appropriate to add 193i double patterning as a potential solution at both the
45 and 32 nm half-pitch. It's not a surprise, actually, that the technique —
 which basically splits a design into two masks to relax the pitch of the
pattern — has been incorporated as a potential solution, given that the
industry has been brimming with positive talk about its potential for at
least a year. But it is not without its headaches, which is why double
patterning also figures prominently in the Difficult Challenges section of
the Lithography chapter.

A double patterning section was dropped in below extreme ultraviolet (EUV)
lithography, with double patterning difficult challenges listed as:

Overlay of multiple exposures, including mask image placement.
Availability of software to split the pattern, apply optical proximity
correction (OPC), and verify the quality of the split while preserving
critical features and maintaining no more than two exposures for arbitrary
designs.

Availability of high-productivity scanner, track and process to maintain low
cost of ownership (CoO).

Resists with independent exposure of multiple passes.

Fab logistics and process control to enable low cycle time impact that
include on-time availability of additional reticles and efficient scheduling
of multiple exposure passes.

Within the Technology Requirements section, double patterning makes an
appearance in both the resist and the mask tables, where requirements have
been added for the near-term and long-term years through 2020. Wafer backside
particle density in photoresists for double patterning does not appear to be
a particular issue, with manufacturable solutions existing even for the 0.14
defects/cm2 required for 2007 and beyond. However, the resist requirements
table shows nothing but red from here on out for defect limits in spin-coated
resist films for double patterning, with a stated requirement of 0.005
defects/cm2.

There's an awful lot of red showing for the double patterning requirements
added to the mask tables. Image placement for double patterning already hit
the brick wall in 2006 at a requirement of 5.7 nm, multipoint, and continues
on through 2020, when the requirement is expected to fall to 1.0 nm. Although
interim solutions are known through 2008 for the difference in CD
mean-to-target for two masks used as a double patterning set, it all turns to
red from there on, as the requirement goes to 2 nm in 2009 and continues on
down to 0.55 nm by 2020.

A small number of other updates have been made to the chapter, particularly
in color changes in the requirements tables that reflect improvements in the
industry.


http://www.semiconductor.net/article/CA6409511.html


--
◣ ◢
  ..
  ◥S

--
※ 發信站: 批踢踢實業坊(ptt.cc) 
◆ From: 140.112.48.60
推 moonshade:有二就有三...
推 gwliao:3次patterning的paper已經報過了......
→ gwliao:而且2次跟3次差很多.  因為3-coloring是NP-C的問題.